A variety of input/output logic standards are in use today including Positive Emitter-Coupled Logic (PECL), Current-Mode Logic (CML), High Speed Transceiver Logic (HSTL), and Low Voltage Differential Signals (LVDS). These configurations may be AC-coupled or DC-coupled.
Each standard defines its own voltage level, type, and termination required for coupling with another stage, or another device. For example, PECL signals generally have voltage levels ranging from (VCC−900 mV) to (VCC−1.7V) where VCC represents a supply voltage. CML signals typically have a voltage level ranging from VCC to (VCC−400 mV). LVDS signals typically have voltage levels ranging from 1 to 1.4V, and HSTL signals typically have voltage levels ranging from 0.3V to 1.1V. Other signal types may use other voltage ranges.
FIGS. 1-6 depict external termination configurations for different logic standards, according to the prior art. As shown in FIG. 1, driver unit 50 generates a CML signal that is terminated using 50Ω resistors 52 and 54 coupled between supply voltage VCC and node 53 and 55, respectively. Nodes 53 and 55 are coupled to output nodes of driver 50 and to input nodes of receiver unit 56. FIG. 2 depicts another termination embodiment for driver unit 57 generating a CML signal, in which a 100Ω resistor 58 is coupled between nodes 59 and 60, which are coupled to output nodes of driver 57 and input nodes of receiver 61.
FIG. 3 depicts a termination configuration for driver 62, generating a PECL output signal using open emitter outputs. Fifty ohm resistors 63 and 64 are coupled between (VCC−2V) supply voltage 65 and nodes 66 and 67, respectively. Nodes 66 and 67 each coupled to an output node of driver unit 62 and an input node of receiver unit 68. FIG. 4 depicts a termination configuration from driver unit 69, generating a PECL output signal using emitter follower outputs. One-hundred ohm resistor 70 is coupled between nodes 71 and 72, which are coupled to output nodes of driver 69 and input nodes of receiver 73.
FIG. 5 depicts a termination configuration for driver 74, generating an LVDS output signal. One-hundred ohm resistor 75 is coupled between nodes 76 and 77, which are coupled to output nodes of driver 75 and input nodes of receiver 78.
FIG. 6 depicts a termination configuration for driver unit 79, generating an HSTL output signal using an open emitter output. Fifty ohm resistors 80 and 81 are coupled between a ground node and nodes 82 and 83, respectively. Nodes 82 and 83 are each coupled to an output node of driver unit 79 and an input node of receiver unit 84.
Accordingly, driver devices need to adapt to a variety of input voltage levels and termination requirements to achieve compatibility. This is typically achieved using multiple input circuits, each able to couple with a particular standard, via a multiplexer. See, for example, FIG. 7 where input circuit 100 and input circuit 105 are coupled to multiplexor 110. Input circuit 100 can receive a PECL input signal, while input circuit 105 can receive an LVDS input signal. Circuit 105 develops a differential input signal between nodes 120 and 125, while circuit 100 develops a differential input signal between nodes 130 and 135. Select signal 115 is applied to multiplexor 110 to determine which differential input signal, the signal at nodes 120 and 125, or that at nodes 130 and 135, is coupled to nodes 140 and 145, which are further coupled to an operative circuit of interest (not shown in FIG. 7 for ease of illustration).
Thus, interfacing from one I/O technology, or standard, to another can therefore be a complex and difficult task. Translators and/or complex termination networks may be necessary for a given device to accept input from a variety of common standards.
Accordingly, there is a need in the art for an input structure that can receive an input according to any of a variety of common standards, including accepting input signals at a variety of voltage levels. Further, such an input structure should be able to provide a variety of termination schemes.
The present invention provides such an input structure.